The present invention relates to an active matrix liquid crystal display (hereinafter referred to as AMLCD) in which a thin film transistor (hereinafter referred to as TFT) array substrate in which TFTs are provided as switching elements is provided and to a method of manufacturing TFT array substrate for AMLCD.
FIG. 18 is a diagram of an equivalent circuit of the AMLCD, and FIG. 19 is a diagram of equivalent circuit of one pixel of the AMLCD.
In FIGS. 18 and 19, reference numeral 21 denotes a TFT, reference numeral 2 denotes a gate line (gate electrode line), reference numeral 9 denotes a source line (source electrode line), reference numeral 22 denotes a pixel capacitance provided by a liquid crystal material in the equivalent circuit (hereinafter referene numeral 22 denotes directly liquid crystal display), reference numeral 23 denotes a storage capacitance, reference numeral 4 denotes a common line for storage capacitance connected to the storage capacitance, reference numeral 24 denotes a connecting portion short-circuiting between a gate line 2 and a source line 9, reference numeral 25 denotes a source side drive circuit which is a drive circuit provided on source lines side, reference numeral 27 denotes a terminal for applying electric voltage to a common line 4.
FIG. 20 is a plan view showing one pixel in a TFT array substrate in which channel etch type TFT is provided. FIGS. 21(a) to 21(f) are sectional views showing a manufacturing step for a portion taken along an Fxe2x80x94F line shown in FIG. 20. In FIG. 20 and FIGS. 21(a) to 21(f), a reference nuemral 1 denotes an insulating substrate made of an insulating material (transparent material can also be employed) such as glass, a reference numeral 3 denotes a gate electrode made of a metal material such as chrome or the like connected to a gate line 2, a reference numeral 4 denotes a common line made of a metal material such as chrome or the like formed on the insulating substrate 1, reference numeral 5 denotes a gate insulating film formed in such a manner that the gate insulating film covers a gate line 2, a gate electrode 3 and a common line 4, reference numeral 6 denotes a semiconductor layer made of semiconductor material such as non-doped amorphous silicon or the like formed through a gate insulating film 5 on a gate electrode 3, reference numeral 7 denotes a contact layer which is formed on the semiconductor layer 6 and is made of a semiconductor film such as silicon or the like doped with impurites such as phosphorus (P) or the like. One portion of the contact layer corresponding to the upper portion of the active area is removed by etching, so that the contact layer includes an etched-off region 8, and is divided into two areas shown by references 7a and 7b depending upon the etched-off region 8. Reference numeral 14 denotes a pixel electrode made of a transparent conductive film such as indium tin oxide (ITO) or the like. The pixel electrode is used to apply a driving voltage upon liquid crystal material. Reference numeral 10 denotes a source electrode formed on a contact layer 7a and connected with source line 9, reference numeral 11 denotes a drain electrode formed on the contact layer 7b, reference numeral 28 denotes a contact hole formed for electrically connecting a gate line 2 with a source line 9, reference numeral 29 denotes a passivation film made of silicon nitride or the like, for covering the whole of outer surface of TFT array substrate.
Manufacturing steps are described below.
As shown in FIG. 21(a), one of chrome (Cr), aluminum (Al), molybdenum (Mo), molybdenum-tungsten (Moxe2x80x94W) or the like is deposited on insulating substrate 1. Then the deposited film is patterned by using a resist (photoresist) formed through photolithography process, in order to form gate line 2, gate electrode 3 and common line 4. As shown in FIG. 21(b), there are continuously formed a gate insulating film 5 composed of silicon nitride or the like, a semiconductor film such as amorphous silicon by, for example, a plasma CVD method. Also, when TFT is n-type TFT, n+-amorphous silicon or the like in which impurities such as phosphorus are doped in high concentration by, for example, a plasma CVD method. Then, the semiconductor layer and contact layer on the semiconductor layer are patterned in order to form a semiconductor layer 6 and contact layer 7 in island like pattern by using a resist formed by photolithography process, by either dry etching method or wet etching method. As shown in FIG. 21(c), a transparent conductive film composed of ITO or the like is deposited. Then the transparent conductive film is patterned by photolithography process, in order to form pixel electrodes 14.
As shown in FIG. 21(d), a contact hole is provided in gate insulating film 5 on the gate line 2 in order to obtain a connecting portion 24 for connecting gate line 2 with source line 9. As shown in FIG. 21(e), one of Cr, Al, Mo, Moxe2x80x94W, or the like is deposted. Then the deposited film is patterned by using a resist formed through photolithography process as a mask, in order to form source line 9, source electrode 10 and drain electrode 11.
Then, an etched-off region a recess 8 of the contact layer 7 is provided in order to remove contact layer 7 from channel area, by etching the contact layer 7 by using source electrode 6 and drain electrode 7 as masks. As shown in FIG. 2(f), a silicon nitride film is deposited by using source elctrode 6 and the drain electrode 7 as masks by a plasma CVD method in order to form passivation film 29. Portions of passivation film 29 on the terminals of gate lines 2 and on the terminals of source lines are removed by using resists formed by a photolithography process, in order to provide connection portion to external circuit. The above-mentioned steps require six photolithography processes to form a TFT array substrate in which channel etch type TFTs are provided.
The functions are described below.
An electric voltage is applied through gate line 2 to gate electrode 3 to let TFT 21 be on state. Then, an image signal is inputted to source line 9; an electric current flows through source electrode 10, semiconductor film 6 and drain electrode 11. TFT 21 comprises source electrode 10, semiconductor film 6 and drain electrode 13. An electric voltage corresponding to the desired image signal is applied through pixel electrode 14 connected with drain electrode 11 to the liquid crystal material 22. A storage capacitance 23 is connected in order to prevent from variation of an electric voltage applied to the liquid crystal material under the influence of storage capacitance 23, corresponding to switching operation of TFT 21. The storage capacitance 23 is provided by common line 4, gate insulating film 5 and pixel electrode 14.
As shown in FIG. 18, gate line 2 and source line 9 are connected electrically at connecting portion 24 at the end portion of the TFT array substrate. This connection of gate line 2 and source line 9 prevents from breakage of TFT by high voltage to gate insulating film 5 caused by static electricity generated in manufacturing steps of TFT array substrate and in rubbing alignment films.
Conventional AMLCD in which channel etch type TFTs are provided is constructed in the above-mentioned manner. Six photolithography processes are required to form TFT array substrate. Thus there arises a problem that the manufacturing cost is high and the throughput is lowered.
The present invention is achieved to solve the above-mentioned problem. The object of the invention is to reduce the number of photolithography processes, to reduce the manufacturing cost and to enhance the throughput in manufacturing steps for TFT array substrate of AMLCD.
According to the present invention there is provided TFT array substrate comprising:
an insulating substrate,
a gate electrode formed on the insulating substrate,
a gate electrode line formed on the insulating substrate,
an insulating film formed on the gate electrode, the gate electrode line and the insulating substrate except for whole of outer surface of the gate electrode and whole of outer surface of the gate electrode line,
a semiconductor layer formed on the insulating film,
a contact layer formed on the semiconductor layer,
a source electrode connected to the contact layer,
a drain electrode which is connected to the contact layer, the contact layer being divided into two portions, one of the two portions corresponding to the source electrode and the other one of the two portions corresponding to the drain electrode,
a source electrode line connected to the source electrode,
an interlayer insulating film formed on the gate electrode, the gate electrode line, the source electrode, the source electrode line and the drain electrode,
a pixel electrode which is formed on the interlayer insulating film and is made of transparent conductive film and is connected electrically to the drain electrode through a first contact hole provided in the interlayer insulating film, and
a connecting line which is made of a same material that of the pixel electrode and connects electrically between the gate electrode line and the source electrode line through a second contact hole provided in the insulating film and a third contact hole provided in the interlayer insulating film.
Preferably, the TFT array substrate further includes
a common line for storage capacitance which is formed through the gate insulating film under the storage capacitance electrode at a same time when the gate electrode and the gate electrode line are formed, and
a storage capacitance electrode which is formed over the common line for storage capacitance, and is formed at a same time when the source electrode, the source electrode line and the gate electrode line are formed, and is connected electrically to the pixel electrode through a contact hole formed in the interlayer insulating film, so that the TFT array substrate includes a storage capacitance between the common line for storage capacitance and the storage capacitance electrode.
Preferably, the TFT array substrate further includes a common line for storage capacitance formed at a same time when the gate electrode and the gate electrode line are formed, so that the TFT array substrate includes a storage capacitance between the common line for storage capacitance and the pixel electrode.
Preferably, the storage capacitance is provided by the storage capacitance electrode and the gate electrode line.
Preferably, the storage capacitance is provided by the gate electrode and the pixel electrode.
Preferably, the interlayer insulating film comprises a thick film.
Preferably, the interlayer insulating film comprises a multi-layer film including a high density film as a lower layer of the multi-layer film.
Preferably, the high density film is composed of silicon nitride.
Preferably, the pixel electrode superposes on at least one of the gate electrode line and the source electrode line.
Preferably, an etching stopper is provided on said semiconductor layer.
According to the present invention there is provided a method of manufacturing a TFT array substrate comprising
an insulating substrate,
a gate electrode formed on the insulating substrate,
a gate electrode line formed on the insulating substrate,
an insulating film formed on the gate electrode, the gate electrode line and the insulating substrate except for whole of outer surface of the gate electrode and whole of outer surface of the gate electrode line,
a semiconductor layer formed on the insulating film,
a contact layer formed on the semiconductor layer,
a source electrode connected to the contact layer,
a drain electrode which is connected to the contact layer, the contact layer being divided into two portions, one of the two portions corresponding to the source electrode and the other one of the two portions corresponding to the drain electrode,
a source electrode line connected to the source electrode,
an interlayer insulating film formed on the gate electrode, the gate electrode line, the source electrode, the source electrode line and the drain electrode,
a pixel electrode which is formed on the interlayer insulating film and is made of transparent conductive film and is connected electrically to the drain electrode through a first contact hole provided in the interlayer insulating film, and
a connecting line which is made of a same material that of the pixel electrode and connects electrically between the gate electrode line and the source electrode line through a second contact hole provided in the insulating film and a third contact hole provided in the semiconductor layer on the source electrode, the insulating film and the interlayer insulating film,
the method comprising steps of:
(a) forming the gate electrode and the gate electrode line on the insulating substrate,
(b) depositing the insulating film on the gate electrode, the gate electrode line and the insulating substrate except for whole of outer surface of the gate electrode and whole of outer surface of the gate electrode line,
(c) forming the semiconductor layer over the gate electrode through the insulating film and forming the contact layer on the semiconductor layer,
(d) forming the source electrode and the drain electrode on the contact layer, and forming the source electrode line and etching the contact layer by using the source electrode and the drain electrode as masks,
(e) depositing the interlayer insulating film on the source electrode, the source electrode line and the drain electrode,
(f) providing simultaneously two of the first contact hole in the insulating film on the gate electrode and in the interlayer insulating film, the second contact hole in the interlayer insulating film on the source electrode line, and the third contact hole in the interlayer insulating film on the drain electrode, and
(g) forming simultaneously the pixel electrode and the connecting line.
Preferably, at least one contact hole of the first contact hole, the second contact hole and the third contact hole, in multi-layer film including at least the interlayer insulating film as a top layer of the multi-layer film is provided by steps of:
(a) providing the one contact hole into the interlayer insulating film, and
(b) etching a lower film of the multi-layer film by using the interlayer insulating film as a mask.
Preferably, an etching stopper is provided on the semiconductor layer and in step (b) the etching stopper is provided after forming the semiconductor layer on the gate electrode and the gate electrode line.
According to the present invention there is provided a method of manufacturing a liquid crystal display comprising a TFT array substrate, an opposite substrate arranged to be opposite to the TFT array substrate, a liquid crystal material interposed between the TFT array substrate and the opposite substrate, a gate IC, a source IC, at least two circuit boards connected to the TFT array substrate,
wherein the TFT array substrate comprises
an insulating substrate,
a gate electrode formed on the insulating substrate,
a gate electrode line formed on the insulating substrate,
an insulating film formed on the gate electrode, the gate electrode line and the insulating substrate except for whole of outer surface of the gate electrode and whole of outer surface of the gate electrode line,
a semiconductor layer formed on the insulating film,
a contact layer formed on the semiconductor layer,
a source electrode connected to the contact layer,
a drain electrode which is connected to the contact layer, the contact layer being divided into two portions, one of the two portions corresponding to the source electrode and the other one of the two portions corresponding to the drain electrode,
a source electrode line connected to the source electrode,
an interlayer insulating film formed on the gate electrode, the gate electrode line, the source electrode, the source electrode line and the drain electrode,
a pixel electrode which is formed on the interlayer insulating film and is made of transparent conductive film and is connected electrically to the drain electrode through a first contact hole provided in the interlayer insulating film, and
a connecting line which is made of a same material that of the pixel electrode and connects electrically at a connecting portion between the gate electrode line and the source electrode line through a second contact hole provided in the insulating film and a third contact hole provided in the semiconductor layer on said source electrode, the insulating film and the interlayer insulating film, the method comprising steps of:
(a) fabricating the TFT array substrate,
(b) providing a first alignment film on the TFT array substrate and performing rubbing operation on the TFT array substrate,
(c) spreading spacers on the first alignment film,
(d) fabricating the opposite substrate,
(e) providing a second alignment film on the opposite substrate and rubbing the second alignment film,
(f) printing sealing agent on prescribed area of the second alignment film,
(g) superposing the opposite substrate on the TFT array substrate, bonding the opposite substate to the TFT array substrate except for a hole for injecting liquid crystal material and injecting the liquid crystal material between the TFT array substrate and the opposite substrate and bonding the hole for injecting liquid crystal material,
(h) cutting the connecting line at the connecting portion,
(i) connecting the gate IC and the source IC to the TFT array substrate,
(j) connecting the circuit boards to the gate IC and to the source IC respectively.
Preferably, in step (f) sealing agent is provided on prescribed area of the first alignment film in place of the second alignment film.